Conventional ROMs, such as 4 Mb and 16 Mb mask ROMs, utilize a NAND-type memory cell structure which allows for high integration. FIG. 1 shows a circuit diagram of a NAND-type mask ROM cell.
A conventional NAND-type mask ROM cell has string lines such as are indicated in FIG. 1 by R1 and R2. String line R1 is made up of string select transistors M1 and M3, and string line R2 is made up of string select transistors M2 and M4. Transistors M1 and M2 are driven by string select line S1, while cell transistors M3 and M4 are driven by string select line S2.
The cell transistors M1, M3, M5, M7, M9 . . . , Mn-1 are serially connected to constitute string line R1, and cell transistors M2, M4, M6, M8, M10 . . . , Mn are serially connected to constitute string line R2.
A bit line is formed by the parallel connection of string lines R1 and R2. Thus, the basic unit of a memory cell array is formed.
Enhancement-type and depletion-type transistors are shown, with the latter being designated by a reference symbol D. Depletion-type transistors are turned on when the voltage of the gate is less than the transistor's threshold voltage, while enhancement-type transistors are turned on when the voltage of the gate is higher than the transistor's threshold voltage. When a transistor is turned off, appreciable current does not flow through it.
For the selection of a particular memory cell, word lines W1, W2, W3 . . . , Wn are driven by voltage sources at a level of Vcc or 0 volts (not shown).
The operation of the conventional NAND-type mask ROM cell will now be described. When the memory cell is in standby mode, a zero voltage, or logic low, is applied to both string selection lines S1 and S2, which thereby floats the bit line because transistors M3 and M2 are turned off. During a read operation, string line R1 may be selected by driving string selection line S2 with the voltage source Vcc (not shown), or a logic high signal, while driving the other string selection line S1 with zero volts.
The cell transistor of string line R1 designated "a" in FIG. 1 is selected when string selection line S1 is driven at a logic low, string selection line S2 is driven at a logic high, word line W2 is driven at a low logic level, and the remaining word lines are driven at a high logic level. Thus, cell transistor "a" is turned off because word line W2 is at a voltage which is below the threshold voltage of an enhancement-mode transistor. The gate voltage of the non-selected cell transistors are higher than the threshold voltage, so the non-selected transistors are turned on because the word lines are being driven at a voltage which is above the threshold voltage level of the enhancement-mode transistor. Thus, whether or not current will flow on the bit line is determined by the level of the voltage at the gate of the selected cell transistor.
Metal oxide semiconductor (MOS) transistors having lightly doped drain (LDD) structure or double diffused drain (DDD) structure are typically used for improved electrical characteristics and reliability in the conventional NAND-type mask ROM. The use of LDD and DDD transistors also allows for the increased integration of the devices.
The source and drain regions of transistors with LDD and DDD structures are formed with low density impurity regions creating a high breakdown voltage and efficiently suppressing the generation of hot-carriers. The low density region together with the channel region bear the voltage drop in the horizontal direction across the channel. The low density impurity regions reduce the maximum value of the electric field in the horizontal direction across the channel, thereby considerably preventing impact ionization which occurs in the vicinity of the drain region. However, the low density impurity region shortens the length of the channel.
When the density of the impurities in the low density region is lowered, the series resistance is increased, which reduces the current driving capability of the device. On the other hand, if the impurity density of the low density region is increased to increase the current driving capability, the horizontal electric field of the channel is increased. Either an increase in series resistance or an increase in the horizontal electric field of the channel reduces the reliability of the device because of the increase in the generation of hot carriers.
FIGS. 2 through 6 are cross-sectional views for explaining a manufacturing method of a conventional transistor having the LDD structure.
A gate oxide film 12 is formed on a P-type semiconductor substrate 11. Then, a polycrystalline silicon (polysilicon) layer is deposited on the gate oxide film 12. A gate electrode 13 is formed by patterning the deposited polysilicon layer using a photo-etching process. Phosphorous 14 is subsequently ion-implanted on the entire surface.
Low density source and drain regions n.sup.- are formed. An oxide film is deposited on the entire surface of the resultant material, which is then anisotropically etched to form sidewall spacers 15 on the side surfaces of the gate electrode 13.
Arsenic 16 is then ion-implanted on the entire surface.
High density source and a drain regions n.sup.+ are then formed, completing the transistor with the LDD structure.
The conventional memory cell uses identically formed transistors with an LDD or a DDD structure in both the the memory cell as well as in the peripheral circuitry. The conventional LDD or DDD transistor suppresses the generation of hot-carriers, however the current driving capability of the device is reduced because of the increased resistance of the low density regions n.sup.-.
Thus, hot-carrier generation is suppressed in the peripheral circuitry, however the memory cell transistor which has less of a problem with hot-carrier generation has its current driving capability reduced because of the increased resistance of the low density n.sup.- region.
The size of the conventional LDD or DDD transistor is influenced by the width of the gate electrode and the sidewall spacer. Therefore, if the current driving capacity of the memory cell transistor is increased by reducing the width of the gate electrode or the sidewall spacer, the punch-through voltage of the peripheral transistor is reduced, worsening the electrical characteristics of the device. Also, if the width of the gate electrode across the channel is reduced in the conventional LDD or DDD memory cell transistor to increase the current capacity, a delay is generated in the device due to the increase of the word line resistance, resulting in slower transition speeds.